1. Field of the Invention
The present invention generally relates to an integrated circuit, in particular, to an integrated circuit with a reduced pad bump area and the manufacturing method thereof.
2. Description of Related Art
IC packages, such as TCP and COF, preceded by a bumping process have been developed for small-scale and high-density integrated circuits. For such an integrated circuit, the required die size much depends on its routing area and pad bump area.
FIG. 1 is a layout diagram illustrating the routing area and the pad bump area of an integrated circuit, and FIG. 2 is a cross-sectional view illustrating the integrated circuit along the line segment AA′ in FIG. 1. Referring to FIG. 1 and FIG. 2, a semiconductor device (exemplified by two MOS transistors in FIG. 1) is disposed on a semiconductor substrate 160. An interconnection layer 170 is disposed above the semiconductor substrate 160 for interconnection of components in the semiconductor device, which may includes one or more conductive layers sandwiched in one or more dielectric layers and connected to the semiconductor device or to each other through plugs. The interconnection layer 170 is topped with a top metal layer 180. The top metal layer 180 may be used as conductive lines 120 such as signal or power lines within its routing area or bonding pads 110 within its pad bump area. A passivation layer 150 is disposed on the interconnection layer 170, which respectively has an opening 140 to expose each of the bonding pads 110. Bumps 130 are then disposed on the passivation layer 150 to connect each of the bonding pads 110 through the corresponding opening 140.
As seen in FIG. 1 and FIG. 2, the bumps 130 are disposed on the passivation layer 150 within a coverage area directly over the corresponding bonding pads 110. Therefore, to meet size limitations on the bumps 130 in certain IC packages, the pad bump area has to be enlarged. Therefore, it is desired to provide an integrated circuit and the manufacturing method thereof, which can meet the size limitations on the bumps and also reduce the pad bump area, thus reducing the required die size and the cost.